The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating fine patterns in a semiconductor device.
As a semiconductor device has been highly integrated, a scaling-down of patterns is required. However, a resolution of a typical photo-exposure apparatus has a limitation to embody fine patterns under 40 nm in a semiconductor device.
Thus, a double patterning method which performs a photolithography process twice is suggested to form the fine patterns. Hereinafter, the double patterning method will be described referring to FIGS. 1A to 1D.
FIGS. 1A to 1D are cross-sectional views of a method for forming typical fine patterns.
Referring to FIG. 1A, a first hard mask layer 11 and a second hard mask layer 12 are sequentially formed over an etch target layer 10.
A photoresist layer is coated over the second hard mask layer 12. The first photoresist layer is patterned by using a photo-exposure and a development process to form first photoresist patterns 13. The first photoresist patterns 13 may have a linewidth corresponding to exposure limitations.
Referring to FIG. 1B, the second hard mask layer 12 is etched by using the first photoresist patterns 13 as an etch barrier to form second hard mask patterns 12A. The first photoresist patterns 13 are removed during forming the second photoresist patterns 12A or separately removed by the subsequent process.
Referring to FIG. 1C, a second photoresist layer is coated over a resultant surface including the second hard mask patterns 12A. The second photoresist layer is patterned using a photo-exposure and a development process to form second photoresist patterns 14. The second photoresist patterns 14 may also have a linewidth corresponding to exposure limitations.
Referring to FIG. 1D, the hard mask layer 11 is etched by using the second hard mask patterns 12A and the second photoresist patterns 14 as an etch barrier to form first hard mask patterns 11A. The second hard mask patterns 12A and the second photoresist patterns 14 are removed during forming the first hard mask patterns 11A or separately removed by the subsequent process.
Although it is not shown, the etch target layer 10 is etched by using the first hard mask patterns 11A as an etch barrier to form etch target patterns.
As above, since the etch target patterns are formed by performing the photolithography process twice, etch target patterns having a fine linewidth are formed despite limitations of a photo-exposure apparatus.
The double patterning method has a limitation described below.
To secure a linewidth uniformity of the etch target patterns, an overlay accuracy of the first photoresist patterns 13 and the second photoresist patterns 14 should be secured. In other words, the second photoresist patterns 14 should be formed to divide a space between the first photoresist patterns 13 into two. However, the typical photo-exposure apparatus cannot accurately control the positions of the first and second photoresist patterns. Also, performing the photolithography process twice causes a cost increase.